https://ee-paper.com/in-ic-design-cloud-is-becoming-the-inevitable-trend-of-future-development/

Process miniaturization is one of the most important characteristics of IC manufacturing technology development. With the improvement of process capability, more devices can be integrated on a chip with the same area, so as to improve the performance of the chip and reduce the unit manufacturing cost. It can be said that the progress of integrated circuit technology is to improve the cost performance of integrated circuit.

However, the increasing complexity of IC design also brings corresponding challenges. For example, in the development process, almost all IC design teams will face the sharp increase of computing resource demand, the difficulty to meet the peak performance requirements of EDA, the consumption cost of deep process data migration, the resource snatch of multi project parallel occurrence and the efficiency impact caused by office location restriction. These problems will directly affect the R & D and development cycle of the chip, and even lead to the poor yield of the chip High, unable to mass production. In addition, a large number of servers consume considerable electricity, and the cost budget is also a big problem.

Therefore, IC design companies increasingly hope to use “cloud capabilities” to shorten turnaround time in advanced process design. In the view of EDA manufacturers, design companies will be able to obtain flexible computing resources and economies of scale by transferring part or all of EDA computing to the cloud. Therefore, under the dual wheel drive of seeking higher design convergence rate and cost-effectiveness, EDA is also exploring a new operation mode – “cloud computing + EDA”.

According to Gartner’s data, the global market size of cloud computing is 64 billion US dollars in 2018, and it is expected to reach 246.1 billion US dollars by the end of 2020, with a compound annual growth rate of 18% from 2019 to 2023. As the key to support the Internet, artificial intelligence and big data, the importance of cloud computing has become increasingly prominent.

More importantly, the cloud in IC design is becoming an inevitable trend in the future.

As one of the leading forces in the EDA market, mentor has seen the long-term development of the market early. The core technology of calibre, its verification platform, has been ready for cloud computing many years ago. At the same time, its latest improvement on cloud security also eases the industry’s concerns about intellectual property (IP) protection, which means that calibre is implemented and used in the cloud processing model The biggest obstacle to technology has been removed.

It is understood that the calibre platform provides a proven ultra remote distributed processing model, which can support the expansion of the core to 4000, greatly reduce the software running time, and enable the IC development team to obtain real-time, available and elastic computing resources, thus shortening the time to market of chip products and accelerating the speed of innovation.

At the same time, using the latest version of calibre software can also optimize memory consumption.

In IC design, it should be noted that SOC design consumes a lot of RAM during verification, and the price of ram is another problem. Even in the cloud, large ram instances are very expensive. Calibre also has a solution to this problem – not only can it reduce the cost of cloud resources, but also can achieve faster processing speed with less RAM CPU.

So, how much turnaround time and operating costs can calibre reduce on the cloud? How can IC design companies find the best practices for their own companies?

In this regard, mentor developed guidelines for cloud usage and proposed best practices for running calibre operations on the cloud. In order to develop and test these guidelines and practices, mentor, together with advanced micro devices, Inc. (AMD) and Microsoft azure (Azure), has jointly launched a project to verify the powerful capabilities of the “calibre on cloud” platform by using AMD epyc server running on the azure public cloud.

In this joint project, mentor used the mass production 7Nm radon insigct ™ Vega20’s final metallization database. The design is AMD’s largest 7Nm chip design, containing more than 13 billion transistors. Experiments show that the physical verification cycle can be shortened by 2.5 times for 7Nm mass production design, and users can also perform design rule checking (DRC) in the way of “best cost performance”

Editor in charge: Tzh